Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate
US8766101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2012 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Mar 6, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A wiring substrate includes an inorganic substrate including a substrate body formed of an inorganic material, a wiring pattern formed on the substrate body, and an external connection terminal being electrically connected to the wiring pattern, an organic substrate that is formed below the inorganic substrate, the organic substrate including an insulating layer and a wiring layer formed on the insulating layer, and a bonding layer interposed between the inorganic substrate and the organic substrate, the bonding layer including a stress buffer layer and a penetration wiring that penetrates the stress buffer layer. A thermal expansion coefficient of the stress buffer layer is greater than a thermal expansion coefficient of the inorganic substrate and less than a thermal expansion coefficient of the organic substrate. The wiring pattern and the wiring layer are electrically connected by way of the penetration wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.