Composite semiconductor device

US8766275B2 · kind B2 · utility

Assignee

• SHARP KABUSHIKI KAISHA · JP

Inventors

• Naoyasu Iketani · Nara, JP
• Tomohiro Nozawa · Shizuoka, JP
• Yoshiaki Nozaki · Iga, JP
• John Twynam · Regensburg, DE
• Hiroshi Kawamura · Osaka, JP
• Keiichi Sakuno · Nara, JP

Key dates

• Filing date: Dec 28, 2010
• Grant date: Jul 1, 2014
• Expiry date: Dec 28, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811

Abstract

This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.