Fin field effect transistor layout for stress optimization

US8766364B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Gerben Doornbos · Kessel-Lo, BE
• Mark van Dal · Linden, BE

Key dates

• Filing date: Aug 31, 2012
• Grant date: Jul 1, 2014
• Expiry date: Aug 31, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

The present disclosure describes a layout for stress optimization. The layout includes a substrate, at least two fin field effect transistors (FinFET) cells formed in the substrate, a FinFET fin designed to cross the two FinFET cells, a plurality of gates formed on the substrate, and an isolation unit formed between the first FinFET cell and the second FinFET cell. The two FinFET cells include a first FinFET cell and a second FinFET cell. The FinFET fin includes a positive charge FinFET (Fin PFET) fin and a negative charge FinFET (Fin NFET) fin. The isolation unit isolates the first FinFET cell from the second FinFET cell without breaking the FinFET fin.