Single metal dual dielectric CMOS device
US8766370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Jul 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor device that includes a semiconductor substrate having a first region and a second region, a pMOS transistor formed over the first region and an nMOS formed over the second region. The pMOS transistor has a gate structure that includes: an interfacial layer formed over the substrate; a AlOx layer formed over the interfacial layer; and a metal layer including Mo or W formed over the AlOx layer. The nMOS transistor has a gate structure that includes: the interfacial layer formed over the substrate; a DyOx layer formed over the interfacial layer; and the metal layer including Mo or W formed over the DyOx layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.