Variable interconnect geometry for electronic packages and fabrication methods
US8766449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2007 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.