Memory controllers to refresh memory sectors in response to writing signals and memory systems including the same
US8767450B2 · kind B2 · utility
1Cited by
13References
14Claims
0Family size
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Key dates
| Filing date | May 13, 2010 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | May 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0088
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.