Non-volatile semiconductor memory device
US8767466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2012 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Jan 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.