Non-volatile semiconductor memory device
US8767477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2013 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Apr 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5635
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number<the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.