Method and apparatus for parallel testing of semiconductor devices
US8768643B2 · kind B2 · utility
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2References
6Claims
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Key dates
| Filing date | May 10, 2011 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Apr 11, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for parallel testing of multiple regions on a substrate used in high performance combinatorial development of new materials and processes are described. The apparatus comprises dedicated hardware for each probe assembly with multiple PC controllers networked using a master/slave configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.