Method and apparatus for achieving non-inclusive cache performance with inclusive caches
US8769209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2010 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Dec 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M<N; in response to receiving an indication that the first cache line is not resident at level M, then evicting the first cache line from the cache at level N; in response to receiving an indication that the first cache line is resident at level M, then retaining the first cache line and choosing a second cache line for potential eviction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.