Bad page management in memory device or system
US8769356B2 · kind B2 · utility
5Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2012 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Nov 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.