Parasitic extraction for semiconductors
US8769462B2 · kind B2 · utility
1Cited by
16References
35Claims
0Family size
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Key dates
| Filing date | Oct 5, 2012 |
| Grant date | Jul 1, 2014 |
| Priority date | — |
| Expiry date | Oct 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.