Method for manufacturing semiconductor device and semiconductor device
US8772175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2012 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Dec 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
Abstract
A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.