III-nitride growth method on silicon substrate
US8772831B2 · kind B2 · utility
2Cited by
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22Claims
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Key dates
| Filing date | Nov 7, 2011 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Jul 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.