Relaxation oscillator
US8773210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2012 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/501
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A relaxation oscillator for generating an output clock signal includes a RC circuit, a bias generation stage, first and second comparator stages, and a logic circuit. The RC circuit generates first and second comparator input signals that are transmitted to the first and second comparator stages. The bias generation stage generates first and second bias voltages that are provided to each of the first and second comparator stages. The first and second comparator stages generate first and second comparator output signals, respectively, based on the first and second comparator input signals and the first and second bias voltages. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.