Vertical switch three-dimensional memory array
US8773881B2 · kind B2 · utility
14Cited by
10References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2010 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Apr 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of forming memory devices include providing a substrate, forming source, channel, and drain layers over the substrate, and patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F2. The channel layer has a doping type different from a doping type of the source layer, and the drain layer has a doping type different from a doping type of the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.