Reducing memory used to store totals in static timing analysis
US8775855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2011 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Sep 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.