Generation of a replay module for simulation of a circuit design
US8775987B1 · kind B1 · utility
2Cited by
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20Claims
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Key dates
| Filing date | Jul 19, 2013 |
| Grant date | Jul 8, 2014 |
| Priority date | — |
| Expiry date | Jul 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches are disclosed for testing a module of a circuit design. The module is simulated a first time using a testbench on a programmed processor. Event data is captured to a first file during the simulating. For each event, the event data describes a signal identifier, an associated signal value, and an associated timestamp. The event data of the first file is transformed into a hardware description language (HDL) replay module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.