Integrated circuits and fabrication methods thereof
US8778767B2 · kind B2 · utility
5Cited by
18References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2011 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Feb 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.