Low phase variation CMOS digital attenuator
US8779870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2011 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Sep 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L5/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low phase variation attenuator uses a combined attenuation path and a phase network to significantly reduce a phase error between a reference signal and an attenuated signal without degrading the insertion loss. A grounded parallel connection of a resistor and a capacitor is employed in series with an attenuation transistor, which is connected to a middle of a two resistor voltage divider. The two resistor voltage divider includes two resistors of equal resistance that are connected in a series connection. The two resistor voltage divider is connected in a parallel connection with a reference transistor, which functions as a main switch for the transmission or attenuation of a radio frequency (RF) signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.