Buffer and control circuit for synchronous memory controller
US8780649B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Mar 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.