Methods and apparatus for using multiple reassembly memories for performing multiple functions
US8782287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Apr 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet processing system comprises first processing circuitry for performing a first function, and first memory circuitry coupled to the first processing circuitry for storing received packets, wherein at least a portion of the packets stored by the first memory circuitry are usable by the first processing circuitry in accordance with the first function. The packet processing system further comprises at least second processing circuitry for performing a second function, and at least second memory circuitry coupled to the second processing circuitry for storing at least a portion of the same packets stored in the first memory circuitry, wherein at least a portion of the packets stored in the second memory circuitry are usable by the second processing circuitry in accordance with the second function. In an illustrative embodiment, the first processing circuitry and the second processing circuitry operate in a packet switching device such as a router. In such case, the first processing circuitry and the second processing circuitry operate between a packet network interface and a switch fabric of the packet switching device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.