Mauricio Calle
14Patents
7h-index
22Co-inventors
62Inventor score
Filing activity: Dec 12, 1997 → Feb 10, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6839797B2 | Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem | Emerging Cross-Sectional Technologies | 24 | Expired |
| US7246102B2 | Method of improving the lookup performance of three-type knowledge base searches | Emerging Cross-Sectional Technologies | 17 | Expired |
| US8497694B2 | On-chip sensor for measuring dynamic power supply noise of the semiconductor chip | Physics | 17 | Active |
| US6944731B2 | Dynamic random access memory system with bank conflict avoidance feature | Emerging Cross-Sectional Technologies | 14 | Expired |
| US6061775A | Apparatus and method for predicting a first microcode instruction of a cache line and using predecode instruction data to identify instruction boundaries and types | Physics | 11 | Expired |
| US5890006A | Apparatus for extracting instruction specific bytes from an instruction | Physics | 11 | Expired |
| US6915480B2 | Processor with packet data flushing feature | Electricity | 10 | Expired |
| US7088719B2 | Processor with packet processing order maintenance based on packet flow identifiers | Electricity | 7 | Expired |
| US7079539B2 | Method and apparatus for classification of packet data prior to storage in processor buffer memory | Electricity | 5 | Expired |
| US6804692B2 | Method and apparatus for reassembly of data blocks within a network processor | Electricity | 4 | Expired |
| US7043544B2 | Processor with multiple-pass non-sequential packet classification feature | Electricity | 4 | Expired |
| US6134650A | Apparatus and method for predicting a first scanned instruction as microcode instruction prior to scanning predecode data | Physics | 3 | Expired |
| US8782287B2 | Methods and apparatus for using multiple reassembly memories for performing multiple functions | Electricity | 1 | Active |
| US7113518B2 | Processor with reduced memory requirements for high-speed routing and switching of packets | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.