Patent · US Active

Control method and controller for DRAM

US8782332B2 · kind B2 · utility

0Cited by
9References
20Claims
0Family size

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Key dates

Filing dateJun 24, 2011
Grant dateJul 15, 2014
Priority date
Expiry dateMar 21, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F13/1673
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, associated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.