Patent · US Active

Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor

US8782374B2 · kind B2 · utility

6Cited by

7References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Lihu Rappoport · Haifa, IL
Chen Koren · Hadera, IL
Franck Sala · Haifa, IL
Oded Lempel · Zichron Ya'akov, IL
Ido Ouziel · Atlit, IL
Ron Gabor · Raanana, IL
Gregory Pribush · Haifa, IL
Lior Libis · Haifa, IL

Key dates

Filing date	Dec 2, 2008
Grant date	Jul 15, 2014
Priority date	—
Expiry date	Mar 26, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.