Branch history with polymorphic indirect branch information
US8782384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2007 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Aug 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a portion or all of a PC of past PIUB instructions. If a hit occurs in this table, the global shift register (GSR) is updated by shifting a portion of the branch target address into the GSR, rather than updating the GSR with a taken/not-taken prediction bit. The stored value in the GSR is input into a hashing function along with the PC in order to index prediction tables such as a pattern history table (PHT), a branch target buffer (BTB), an indirect target array, or other. The updated value due to the PIUB instruction improves the accuracy of the prediction tables.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.