Automatic load balancing for heterogeneous cores
US8782645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2011 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Dec 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5083
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficient automatic scheduling of the execution of work units between multiple heterogeneous processor cores. A processing node includes a first processor core with a general-purpose micro-architecture and a second processor core with a single instruction multiple data micro-architecture. A computer program comprises one or more compute kernels, or function calls. A compiler computes pre-runtime information of the given function call. A runtime scheduler produces one or more work units by matching each of the one or more kernels with an associated record of data. The scheduler assigns work units either to the first or to the second processor core based at least in part on the computed pre-runtime information. In addition, the scheduler is able to change an original assignment for a waiting work unit based on dynamic runtime behavior of other work units corresponding to a same kernel as the waiting work unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.