Non-planar semiconductor device having channel region with low band-gap cladding layer

US8785909B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Marko Radosavljevic · Portland, US
• Gilbert Dewey · Beaverton, US
• Benjamin Chu-Kung · Portland, US
• Dipanjan Basu · Hillsboro, US
• Sanaz K. Gardner · Portland, US
• Satyarth Suri · Hillsboro, US
• Ravi Pillarisetty · Portland, US
• Niloy Mukherjee · Beaverton, US
• Han Wui Then · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Sep 27, 2012
• Grant date: Jul 22, 2014
• Expiry date: Sep 27, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.