Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same

US8786066B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• John S. Guzek · Chandler, US
• Ravi Kiran Nalla · San Jose, US
• Javier Soto Gonzalez · Chandler, US
• Drew W. Delaney · Chandler, US
• Suresh Pothukuchi · Chandler, US
• Mohit Mamodia · Chandler, US
• Edward Zarbock · Gilbert, US
• Johanna M. Swan · Scottsdale, US

Key dates

• Filing date: Sep 24, 2010
• Grant date: Jul 22, 2014
• Expiry date: Oct 24, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.