Fast analog memory cell readout using modified bit-line charging configurations
US8787057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2012 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Dec 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for data storage includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.