Yael Shur
17Patents
4h-index
18Co-inventors
49Inventor score
Filing activity: Dec 10, 2012 → Feb 20, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9330783B1 | Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block | Physics | 14 | Active |
| US10008278B1 | Memory block usage based on block location relative to array edge | Physics | 11 | Active |
| US8773905B1 | Identifying and mitigating restricted sampling voltage ranges in analog memory cells | Physics | 10 | Active |
| US9390809B1 | Data storage in a memory block following WL-WL short | Physics | 8 | Active |
| US8717826B1 | Estimation of memory cell wear level based on saturation current | Physics | 4 | Active |
| US8824214B2 | Inter-word-line programming in arrays of analog memory cells | Physics | 3 | Active |
| US10936456B1 | Handling malfunction in a memory system comprising a nonvolatile memory by monitoring bad-block patterns | Physics | 2 | Active |
| US9594615B2 | Estimating flash quality using selective error emphasis | Physics | 2 | Active |
| US8787057B2 | Fast analog memory cell readout using modified bit-line charging configurations | Physics | 1 | Active |
| US10332608B2 | Memory block usage based on block location relative to array edge | Physics | 0 | Active |
| US9230680B2 | Applications for inter-word-line programming | Physics | 0 | Active |
| US8837214B2 | Applications for inter-word-line programming | Physics | 0 | Active |
| US9236132B2 | Mitigating reliability degradation of analog memory cells during long static and erased state retention | Physics | 0 | Active |
| US9105311B2 | Inter-word-line programming in arrays of analog memory cells | Physics | 0 | Active |
| US9672925B2 | Storage in charge-trap memory structures using additional electrically-charged regions | Electricity | 0 | Active |
| US9455040B2 | Mitigating reliability degradation of analog memory cells during long static and erased state retention | Physics | 0 | Active |
| US9312017B2 | Storage in charge-trap memory structures using additional electrically-charged regions | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.