Floating-body/gate DRAM cell
US8787072B2 · kind B2 · utility
6Cited by
9References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | May 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.