Semiconductor memory device comprising three-dimensional memory cell array
US8787082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2012 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Aug 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.