Programmable atomic memory using stored atomic procedures
US8788794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2010 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Jan 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/467
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets a set of one or more atomicity criteria, including that no instruction in the sequence instructs the processing core to access shared memory. After validating the sequence, the processing core executes the sequence as a single atomic memory transaction, such as by locking a source cache line that stores shared memory data, executing the validated sequence of instructions, storing a result of the sequence into the source cache line, and unlocking the source cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.