Methods and apparatus to perform error detection and correction
US8788904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2011 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Mar 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example methods, apparatus, and articles of manufacture to perform error detection and correction are disclosed. A disclosed example method involves enabling a memory controller to operate in one of a tagged memory mode or a non-tagged memory mode. In addition, when the tagged memory mode is enabled in the memory controller, a five-error-correction-six-error-detection per-burst mode is selected to perform error correction on data. When the non-tagged memory mode is enabled in the memory controller, one of a six-error-correction-seven-error-detection per-burst mode or a single-error-correction-dual-error-detection per-transfer mode is selected based on a pattern of error types in the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.