Patent · US Active

Gate array architecture with multiple programmable regions

US8788984B2 · kind B2 · utility

1Cited by

3References

18Claims

0Family size

Assignee

BaySand Inc. · US

Inventors

Jonathan Park · San Jose, US
Salah M Werfelli · معلمی نژاد, US
WeiZhi Kang · Kuala Krai, MY
Wan Tat Hooi · Kuala Kangsar, MY
Kok Siong Tee · Bukit Mertajam, MY
Jeremy Jia Jian Lee · Kuala Kangsar, MY

Key dates

Filing date	Aug 20, 2013
Grant date	Jul 22, 2014
Priority date	—
Expiry date	Aug 20, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/988
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.