Method of forming semiconductor device having self-aligned plug
US8790976B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2013 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Jul 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.