Through silicon via wafer, contacts and design structures
US8791016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2012 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Sep 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the via formed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.