Substrate breakdown voltage improvement for group III-nitride on a silicon substrate
US8791504B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2011 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Jun 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit structure includes a substrate, a nucleation layer of undoped aluminum nitride, a graded buffer layer comprising aluminum, gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant, a ungraded buffer layer comprising gallium, nitrogen, one of silicon and oxygen, and a p-type conductivity dopant without aluminum, and a bulk layer of undoped gallium nitride over the ungraded buffer layer. The various dopants in the graded buffer layer and the ungraded buffer layer increases resistivity and results in layers having an intrinsically balanced conductivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.