Wafer backside interconnect structure connected to TSVs
US8791549B2 · kind B2 · utility
21Cited by
82References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2010 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Jun 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.