Reliable message transport network
US8792512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2007 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Apr 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0096
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.