Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulation
US8793469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2010 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Nov 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.