System and method for determining power leakage of electronic circuit design
US8793641B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2013 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | May 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for determining power leakage of an electronic circuit design that includes a plurality of digital logic elements, using an electronic design automation (EDA) tool that includes a processor and an automatic test pattern generation (ATPG) tool for generating multiple sets of input value strings. The ATPG tool generates test patterns that include input value strings for simulating each digital logic element of the circuit design independently. A mapping between generated output values and corresponding input values is stored in a look up table (LUT). Thereafter, the ATPG tool generates test patterns that include input value strings for simulating the real-time behavior of the circuit design. The processor determines power leakage of the circuit design based on probability of occurrence of each unique input value string at the input of each digital logic element and corresponding predetermined power leakage values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.