Loop parallelization based on loop splitting or index array
US8793675B2 · kind B2 · utility
9Cited by
20References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2010 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Jul 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus to provide loop parallelization based on loop splitting and/or index array are described. In one embodiment, one or more split loops, corresponding to an original loop, are generated based on the mis-speculation information. In another embodiment, a plurality of subloops are generated from an original loop based on an index array. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.