Low cost die-to-wafer alignment/bond for 3d IC stacking
US8796073B2 · kind B2 · utility
2Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2008 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.