Patent · US Active

System and method for electronic testing of partially processed devices

US8797056B2 · kind B2 · utility

1Cited by
0References
21Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 22, 2011
Grant dateAug 5, 2014
Priority date—
Expiry dateMar 22, 2031

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2225/06596
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.