Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration
US8799588B2 · kind B2 · utility
4Cited by
3References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 8, 2012 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Aug 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.