Forward progress mechanism for stores in the presence of load contention in a system favoring loads
US8799589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2012 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Nov 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.