3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits
US8799710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2012 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Jan 24, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3-D) processor system includes a first processor chip and a second processor chip in a stacked configuration. The first processor chip includes a first processor having a first set of state registers. The second processor chip includes a second processor having a second set of state registers that corresponds to the first set of state registers. The first and second processors are connected through vertical connections between the first and second processor chips. A mode control circuit operates the processor system in one of a plurality of operating modes. In one mode of operation, the first processor is active and the second processor is inactive, and the first processor operates at a speed greater than a maximum safe speed of the first processor, and the first processor uses the second set of state registers of the second processor to checkpoint a state of the first processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.