Michael B. Healy
38Patents
5h-index
25Co-inventors
65Inventor score
Filing activity: May 15, 2007 → Dec 5, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9471423B1 | Selective memory error reporting | Physics | 17 | Active |
| US7441833B1 | Arrangement and method for converting of single panel sunroofs into double panel sunroofs and component parts thereof | Performing Operations; Transporting | 12 | Active |
| US10019312B2 | Error monitoring of a memory device containing embedded error correction | Electricity | 7 | Active |
| US9734885B1 | Thermal-aware memory | Emerging Cross-Sectional Technologies | 6 | Active |
| US9761294B1 | Thermal-aware memory | Physics | 6 | Active |
| US9898218B2 | Memory system with switchable operating bands | Emerging Cross-Sectional Technologies | 4 | Active |
| US9690649B2 | Memory device error history bit | Physics | 3 | Active |
| US9606851B2 | Error monitoring of a memory device containing embedded error correction | Electricity | 3 | Active |
| US9940457B2 | Detecting a cryogenic attack on a memory device with embedded error correction | Physics | 3 | Active |
| US9626242B2 | Memory device error history bit | Physics | 3 | Active |
| US9747148B2 | Error monitoring of a memory device containing embedded error correction | Electricity | 3 | Active |
| US8799710B2 | 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits | Emerging Cross-Sectional Technologies | 2 | Active |
| US9684555B2 | Selective memory error reporting | Physics | 2 | Active |
| US10740003B2 | Latency-agnostic memory controller | Physics | 1 | Active |
| US9383411B2 | Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers | Physics | 1 | Active |
| US9389876B2 | Three-dimensional processing system having independent calibration and statistical collection layer | Physics | 1 | Active |
| US10613774B2 | Partitioned memory with locally aggregated copy pools | Physics | 0 | Active |
| US9257152B2 | Memory architectures having wiring structures that enable different access patterns in multiple dimensions | Electricity | 0 | Active |
| US10063263B2 | Extended error correction coding data storage | Physics | 0 | Active |
| US11481158B2 | Enabling compression based on queue occupancy | Physics | 0 | Active |
| US9336144B2 | Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations | Emerging Cross-Sectional Technologies | 0 | Active |
| US9190118B2 | Memory architectures having wiring structures that enable different access patterns in multiple dimensions | Physics | 0 | Active |
| US9298672B2 | 3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components | Emerging Cross-Sectional Technologies | 0 | Active |
| US9569402B2 | 3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components | Emerging Cross-Sectional Technologies | 0 | Active |
| US8826073B2 | 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.